Integrated circuit memory devices are widely used in consumer and commercial applications. One widely used integrated circuit memory device is a synchronous Dynamic Random Access Memory (synchronous DRAM device. Synchronous DRAMs may be used for the main memory of a computer system, and also may be used in graphics applications. In particular, a byte-wide synchronous DRAM, i.e., a synchronous DRAM having a data path width of X16 or wider, may be used in graphics applications. Here, X16 denotes that 16 bits of data can be simultaneously input or output. Synchronous DRAMs may include a data masking function to mask data that is input via data input and output pins (typically called "DQ pins") from an external source. The data masking generally is performed in units of 8 bits.
For example, in the case of a synchronous DRAM having a data path width of X16, there are generally two data masking pins (typically called "DQM pins") from which data masking signals are input. These DQM pins comprise a lower DQM (LDQM) pin and an upper DQM (UDQM) pin. The LDQM pin masks data input via data input and output pins DQ0 through DQ7, i.e., the lower 8 bits of 16 bits that are input via 16 data input and output pins DQ1 through DQ15. The UDQM pin masks the upper 8 bits, i.e., data input via data input and output pins DQ8 through DQ15. It will be understood that as used herein, the term pins includes any input/output structure for an integrated circuit device and can include pads, optical input/output structures and other conventional input/output structures.
In the case of a synchronous DRAM having a data path width of X32, there are generally four data masking pins DQM0 through DQM3 via which data masking signals are input. The data masking pin DQM0 masks 8 bits of 32 bits that are input via 32 data input and output pins DQ0 through DQ31, i.e., data that is input via data input and output pins DQ0 through DQ7. The data masking pin DQM1 masks 8 bits that are input via data input and output pins DQ8 through DQ15, the data masking pin DQM2 masks 8 bits that are input via data input and output pins DQ16 through DQ23, and the data masking pin DQM3 masks 8 bits that are input via data input and output pins DQ24 through DQ31.
FIG. 1 is a block diagram showing DQ allocation and bank allocation in a conventional 2M(Mega)X32 DRAM. Referring to FIG. 1, the 2MX32 DRAM is divided into four banks, i.e., bank A through bank D, each comprised of 16M blocks. Accordingly, 32 DQ pins, which are controlled by four data masking pins, all are allocated to one column selection line (CSL).
In a highly integrated DRAM having such a configuration, when a data masking signal is input to any one data masking pin upon masking of read data, output buffers connected to 8 data input and output pins corresponding to the data masking signal are disabled, thereby masking the read data. When a data masking signal is input to any one data masking pin upon masking of write data, 8 input and output line pairs connected to 8 data input and output pins corresponding to the data masking signal are precharged, and input and output line drivers for driving the input and output line pairs are turned off. In this way, the write data is masked.
However, in a highly integrated DRAM having such a configuration, the input and output line pairs typically are formed of tungsten (W), so that the resistances of the input and output line pairs may increase with a reduction in the size of the integrated circuit. Thus, the input and output line pairs may not be precharged sufficiently upon masking of write data. Hence, masking of write data may not be performed properly.